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a ad6624 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. rev. b the ad6624 is part of analog devices?softcell multicarrier transceiver chipset designed for compatibility with analog devices?family of high sample rate if sampling adcs (ad6640/ ad6 644 12- and 14-bit). the softcell receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and c hannel selection. this architecture eliminates redundant radios in wireless base station applications. high dynamic range decimation filters offer a wide range of decimation rates. the ram-based architecture allows easy reconfiguration for multimode applications. the decimating filters remove unwanted signals and noise from t he channel of interest. when the channel of interest occupies less bandwidth than the input signal, this rejection of out-of-band n oise is called ?rocessing gain.?by using large decimation factors, this ?rocessing gain?can improve the snr of the adc by 30 db or more. in addition, the programmable ram coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, cost- effective filter. the ad6624 is compatible with standard adc converters such as the ad664x, ad9042, ad943x, and the ad922x families of data converters. the ad6624 is also compatible with the ad6600 diversity adc, providing a cost and size reduction path. four-channel, 80 msps digital receive signal processor (rsp) functional block diagram ch a nco rcic2 resampler cic5 ram coefficient filter 16 bits 18 bits 20 bits 24 bits input matrix serial and microport ina[13:0] expa[2:0] iena lia-a lia-b synca syncb syncc syncd inb[13:0] expb[2:0] ienb lib-a lib-b sdin[3:0] sdo[3:0] dr[3:0] sdfs[3:0] sdfe[3:0] sclk[3:0] mode ds ( rd ) cs rw ( wr ) dtack (rdy) a[2:0] d[7:0] ch b nco rcic2 resampler cic5 ram coefficient filter ch c nco rcic2 resampler cic5 ram coefficient filter ch d nco rcic2 resampler cic5 ram coefficient filter external sync circuitry jtag interface b uilt-in self-test features 80 msps wide band inputs (14 linear bits plus 3 rssi) dual high speed data input ports four independent digital receivers in single package digital resampling for noninteger decimation rates programmable decimating fir filters programmable attenuator control for clip prevention and external gain ranging via level indicator flexible control for multicarrier and phased array 3.3 v i/o, 2.5 v cmos core user-configurable built-in self-test (bist) capability jtag boundary scan applications multicarrier, multimode digital receivers gsm, is136, edge, phs, is95 micro and pico cell systems wireless local loop smart antenna systems software radios in-building wireless telephony product description the ad6624 is a four-channel (quad) digital receive signal processor (rsp) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable-coefficient decimating filter.
rev. b ad6624 e2e table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product description . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 specifications/characteristics . . . . . . . . . . . . . 3 general timing characteristics . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . 9 pin function descriptions . . . . . . . . . . . . . . . . . 11 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 example filter response . . . . . . . . . . . . . . . . . . . 14 input data ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 gain switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 input data scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 scaling with fixed-point adcs . . . . . . . . . . . . . . . . . . . . 16 scaling with floating-point or gain-ranging adcs . . . . 16 numerically controlled oscillator . . . . . 17 frequency translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 nco frequency hold-off register . . . . . . . . . . . . . . . . . 17 phase offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 nco control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 phase dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 amplitude dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clear phase accumulator on hop . . . . . . . . . . . . . . . . . . 17 input enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 mode 00: blank on ien low . . . . . . . . . . . . . . . . . . . . . 17 mode 01: clock on ien high . . . . . . . . . . . . . . . . . . . . 18 mode 10: clock on ien transition to high . . . . . . . . . . 18 mode 11: clock on ien transition to low . . . . . . . . . . . 18 wb input select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sync select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 second order rcic filter . . . . . . . . . . . . . . . . . . . 18 rcic2 rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 example calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 decimation and interpolation registers . . . . . . . . . . . . . . 19 rcic2 scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fifth order cascaded integrator comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 cic5 rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ram coefficient filter . . . . . . . . . . . . . . . . . . . . . 20 rcf decimation register . . . . . . . . . . . . . . . . . . . . . . . . 21 rcf decimation phase . . . . . . . . . . . . . . . . . . . . . . . . . . 21 rcf filter length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 rcf output scale factor and control register . . . . . . . . 21 user-configurable built-in self-test (bist) 22 ram bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 channel bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chip synchronization . . . . . . . . . . . . . . . . . . . . . . 22 start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 serial output data port . . . . . . . . . . . . . . . . . . . 24 serial output data format . . . . . . . . . . . . . . . . . . . . . . . 24 serial data frame (serial bus master) . . . . . . . . . . . . . . . 24 serial data frame (serial cascade) . . . . . . . . . . . . . . . . . 25 configuring the serial ports . . . . . . . . . . . . . . . . . . . . . . . 25 serial port data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 serial port to dsp interconnection . . . . . . . . . . . . . . . . . 25 serial slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 serial ports cascaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 serial output frame timing (master and slave) . . . . . . . 26 serial port timing specifications . . . . . . . . . . . . . . . . . . . 26 sbm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 sclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sdin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sdfs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sdfe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 serial word length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sdfs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mapping rcf data to the bist registers . . . . . . . . . . . . 29 0x00e0x7f: coefficient memory (cmem) . . . . . . . . . . . 29 0x80: channel sleep register . . . . . . . . . . . . . . . . . . . . . 30 0x81: soft_sync register . . . . . . . . . . . . . . . . . . . . . . . 30 0x82: pin_sync register . . . . . . . . . . . . . . . . . . . . . . . . 30 0x83: start hold-off counter . . . . . . . . . . . . . . . . . . . . . 30 0x84: nco frequency hold-off counter . . . . . . . . . . . . 30 0x85: nco frequency register 0 . . . . . . . . . . . . . . . . . . 30 0x86: nco frequency register 1 . . . . . . . . . . . . . . . . . . 30 0x87: nco phase offset register . . . . . . . . . . . . . . . . . . 30 0x88: nco control register . . . . . . . . . . . . . . . . . . . . . . 30 0x90: rcic2 decimation e 1 (m rcic2 e1) . . . . . . . . . . . . . 31 0x91: rcic2 interpolation e 1 (l rcic2 e1) . . . . . . . . . . . . 31 0x92: rcic2 scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 0x94: cic5 decimation e 1 (m cic5 e1) . . . . . . . . . . . . . . 31 0x95: cic5 scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 0xa0: rcf decimation e 1 (m rcf e1) . . . . . . . . . . . . . . . 31 0xa1: rcf decimation phase (p rcf ) . . . . . . . . . . . . . . . 31 0xa2: rcf number of taps minus one (n rcf -1) . . . . . 31 0xa3: rcf coefficient offset (co rcf ) . . . . . . . . . . . . . . 31 0xa4: rcf control register . . . . . . . . . . . . . . . . . . . . . . 31 0xa5: bist register for i . . . . . . . . . . . . . . . . . . . . . . . . 32 0xa6: bist register for q . . . . . . . . . . . . . . . . . . . . . . . 32 0xa7: bist control register . . . . . . . . . . . . . . . . . . . . . 32 0xa8: ram bist control register . . . . . . . . . . . . . . . . 32 0xa9: serial port control register . . . . . . . . . . . . . . . . . 32 microport control . . . . . . . . . . . . . . . . . . . . . . . . 33 external memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 access control register (acr) . . . . . . . . . . . . . . . . . . . . 33 external memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 channel address register (car) . . . . . . . . . . . . . . . . . . . 34 soft_sync control register . . . . . . . . . . . . . . . . . . . . 34 pin_sync control register . . . . . . . . . . . . . . . . . . . . . . 34 sleep control register . . . . . . . . . . . . . . . . . . . . . . . . . 34 data address registers . . . . . . . . . . . . . . . . . . . . . . . . . . 35 write sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 read sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 read/write chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 intel nonmultiplexed mode (inm) . . . . . . . . . . . . . . . . . 35 motorola nonmultiplexed mode (mnm) . . . . . . . . . . . . 35 input port control registers . . . . . . . . . . . . . . . . . . . . . . 35 serial port control . . . . . . . . . . . . . . . . . . . . . . . . 36 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . 36 internal write access . . . . . . . . . . . . . . . . . . . . . . 37 write pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 internal read access . . . . . . . . . . . . . . . . . . . . . . . 37 read pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 38
rev. b e3e ad6624 recommended operating conditions test ad6624as parameter level min typ max unit vdd iv 2.375 2.5 2.675 v vddio iv 3.0 3.3 3.6 v t ambient iv e40 +25 +70 () () + ( =) ( =) =(==) =(= ==) = = (= 5%, vddio = 3.3 v 10%. all specifications t a = t min to t max , unless otherwise noted.)
rev. b e4e ad6624especifications general timing characteristics 1, 2 test ad6624as parameter (conditions) temp level min typ max unit clk timing requirements : t clk clk period full i 12.5 ns t clkl clk width low full iv 4.5 0.5 reset timing requirement : t resl reset w input wideband data timing requirements : t si input to level indicator output switching characteristic : t dli () sync timing requirements : t ss sync (a, b, c, d) to () serial port timing requirements ( sbm = 1 ): switching characteristics : 3 t dsclk1 () () () () + + + input characteristics : t ssi sdi to serial port timing requirements ( sbm = 0 ): switching characteristics : 3 t sclk sclk period full iv 16 ns t sclkl sclk low time (when sdiv = 1, divide by 1) full iv 5.0 ns t sclkh sclk high time (when sdiv = 1, divide by 1) full iv 5.0 ns t dsdfe input characteristics : t ssf sdfs to = () ()
rev. b e5e ad6624 microprocessor port timing characteristics 1, 2 test ad6624as parameter (conditions) temp level min typ max unit microprocessor port, mode inm (mode = 0) mode inm write timing : t sc control 3 to wr( rw ) rd( dtack )t sa ad wr (rw)st a adrd( dtack )t drd wr (rw)rd( dtack )d acc wr (rw)rd( dtack )d mode inm read timing : t sc control 3 to rd ( ds )st a adt drd rd ( ds )rd( dtack )d acc rd ( ds )rd( dtack )d (=) mode mnm write timing : t sc control 3 to ds ( rd ) dtack (rd)t rw rw( wr ) dtack (rd)t sa adrw( wr )st a adrw( wr )t acc rw( wr ) dtack (rd)d mode mnm read timing : t sc control 3 to ds ( rd )st a adt d dtsd acc ds ( rd ) dtack (rd)d = ( wr ), ds ,( rd ), cs s
rev. b ad6624 e6e timing diagrams clk lia-a lia-b lib-a lib-b t dli t clk t clkl t clkh figure 1. level indicator output switching characteristics r eset t ssf figure 2. reset tr e t s tr s s s s ss s s s ss ee s s s ss s ss s se ss s t se ss ss
rev. b ad6624 e7e sclk sdo sdfe t dsdo t dsdfe q 1 q 0 i 14 i 15 figure 8. sdo, sdfe switching characteristics clk dr t ddr figure 9. clk, dr switching characteristics sclk dr t dsdr figure 10. sclk, dr switching characteristics sclk sdfs t ssf t hsf figure 11. sdfs timing requirements (sbm = 0) clk in[13:0] exp[2:0] ien t si t hi figure 12. input timing for a and b channels clk synca syncb syncc syncd t ss t hs figure 13. sync timing inputs
rev. b ad6624 e8e timing diagrams?inm microport mode timing diagrams?mnm microport mode clk rd ( ds ) wr (rw) cs a[2:0] d[7:0] rdy ( dtack ) t sc t hc t hwr t sam t sam t ham t drdy va l i d data va lid address t ham t acc notes 1. t acc access time depends on the address accessed. access time is measured from fe of wr to the re of rdy. 2. t acc requires a maximum 9 clk periods. figure 14. inm microport write timing requirements clk rd ( ds ) wr (rw) a[2:0] d[7:0] rdy ( dtack ) t sc t sam t zd t drdy va l id data va lid address t acc t hc cs t zd t ham notes 1. t acc access time depends on the address accessed. access time is measured from fe of wr to the re of rdy. 2. t acc requires a maximum of 13 clk periods and applies to a[2:0] = 7, 6, 5, 3, 2, 1 t dd figure 15. inm microport read timing requirements clk ds ( rd ) cs a[2:0] d[7:0] dtack (rdy) t sc t hc t hrw t sam t sam t ham va l i d data va lid address t ham t acc notes 1. t acc access time depends on the address accessed. access time is measured from fe of ds to the fe of dtack . 2. t acc requires a maximum 9 clk periods. rw ( wr ) t ddtack t hds figure 16. mnm microport write timing requirements clk rd ( ds ) wr (rw) a[2:0] d[7:0] dtack ( rdy) t sc t sam t zd va l id data va lid address t acc t hc cs t zd t ham t dd t ddtack t hds notes 1. t acc access time depends on the address accessed. access time is measured from fe of ds to the fe of dtack . 2. t acc requires a maximum 13 clk periods. figure 17. mnm microport read timing requirements
rev. b ad6624 e9e absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 v input voltage . . . . . . . . . . . . e0.3 v to +5.3 v (5 v tolerant) output voltage swing . . . . . . . . . . e0.3 v to vddio + 0.3 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . 125 + () = = = () + () ()
rev. b ad6624 e10e pin configuration 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 100 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier top view (not to scale) vssio inb6 inb7 inb8 inb9 vddio inb10 inb11 inb12 inb13 vdd expb2 expb1 expb0 dr3 vss sdfe3 sdin3 sdo3 sdfs3 syncd syncc syncb synca vdd reset d7 d6 d5 d4 vss d3 d2 d1 vdd d0 ds ( rd ) dtack /rdy rw( wr) vss sdo2 sdfs2 sclk2 dr1 sdfe1 vdd sdin1 sdo1 sdfs1 sclk1 vssio dr0 sdiv2 sdiv3 sbm0 chip_id0 vss chip_id1 chip_id2 chip_id3 vss inb5 inb4 inb3 inb2 inb1 vdd inb0 ienb lib-b lib-a vss clk expa0 expa1 expa2 vdd ina13 ina12 ina11 ina10 vddio ina9 ina8 ina7 ina6 vssio ina5 ina4 ina3 ina2 lia-a vddio mode a2 a1 a0 vssio vssio tdi vddio vddio sclk3 dr2 sdfe2 sdin2 vssio sdfe0 sdin0 sdo0 vddio sdfs0 sclk0 sdiv0 sdiv1 vdd ad6624 ina1 ina0 iena lia-b vdd vss tdo tms tclk trst cs vss
rev. b ad6624 e11e pin function descriptions pin no. mnemonic type function 1, 12, 38, 50, 65, 76, 102, 113 vss g ground 2e6 inb[5:1] 1 ib input data (mantissa) 7, 17, 32, 44, 54, 81, 96, 118 vdd p 2.5 v supply 8i nb0 1 ib input data (mantissa)?lsb 9 ienb 2 i input enable?input b 10 lib-b o level indicator?input b, interleaved?data b 11 lib-a o level indicator?input b, interleaved?data a 13 clk i input clock 14e16 expa[0:2] 1 ia input data (exponent) 18e21 ina[13:10] 1 ia input data (mantissa) 22, 59, 71, 86, 108, 123 vddio p 3.3 v supply 23e26 ina[9:6] 1 ia input data (mantissa) 27, 39, 64, 91, 103, 128 vssio g ground 28e31 ina[5:2] 1 ia input data (mantissa) 33e34 ina[1:0] 1 ia input data (mantissa) 35 iena 2 i input enable?input a 36 lia-b o level indicator?input a, interleaved?data b 37 lia-a o level indicator?input a, interleaved?data a 40 syncd 1 ia ll sync pins go to all four output channels 41 syncc 1 ia ll sync pins go to all four output channels 42 syncb 1 ia ll sync pins go to all four output channels 43 synca 1 ia ll sync pins go to all four output channels 45 reset a r d t d d t d d t ds ds ( rd ) ads(ar) dtack (rd) t ada(s) rw( wr ) rw(aw) de s a a cs c s trst t r tck t c ts t s td t td td t d cd c ds cd c dss s sc sd scdc sd scdc sck scc sds sdsc sd t sdc sd sdc sde sdec dr drc
rev. b ad6624 e12e pin function descriptions (continued) pin no. mnemonic type function 92 sclk1 1 i/o bidirectional serial clock?channel 1 93 sdfs1 1 i/o bidirectional serial data frame sync?channel 1 94 sdo1 1 o/t serial data output?channel 1 95 sdin1 1 i serial data input?channel 1 97 sdfe1 o serial data frame end?channel 1 98 dr1 o output data ready indicator?channel 1 99 sclk2 1 i/o bidirectional serial clock?channel 2 100 sdfs2 1 i/o bidirectional serial data frame sync?channel 2 101 sdo2 1 o/t serial data output?channel 2 104 sdin2 1 i serial data input?channel 2 105 sdfe2 o serial data frame end?channel 2 106 dr2 o output data ready indicator?channel 3 107 sclk3 1 i/o bidirectional serial clock?channel 3 109 sdfs3 1 i/o bidirectional serial data frame sync?channel 3 110 sdo3 1 o/t serial data output?channel 3 111 sdin3 1 i serial data input?channel 3 112 sdfe3 o serial data frame end?channel 3 114 dr3 o output data ready indicator?channel 3 115e117 expb[0:2] 1 ib input data (exponent) 119e122 inb[13:10] 1 ib input data (mantissa) 124e127 inb[9:6] 1 ib input data (mantissa) notes 1 pins with a pull-down resistor of nominal 70 k ? ? =====
rev. b ad6624 e13e architecture the ad6624 has four signal processing stages: a frequency translator, second order resampling cascaded integrator comb fir filters (rcic2), a fifth order cascaded integrator comb fir filter (cic5), and a ram coefficient fir filter (rcf). multiple modes are supported for clocking data into and out of the chip, and provide flexibility for interfacing to a wide variety of digitizers. programming and control is accomplished via serial and microprocessor interfaces. frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (nco). real data entering t his stage is separated into in-phase (i) and quadrature (q) components. t his stage translates the i nput signal from a digital intermediate frequency (if) to digital baseband. phase and am plitude dither may be enabled on-chip to improve spurious performance of the nco. a phase-offset word is available to create a known phase relationship between m ultiple ad 6624s or between channels. following frequency translation is a resampling, fixed- coeffi cient, h igh speed, second order, resampling cascade integrator comb (rcic2) filter that reduces the sample rate based on the ratio between the decimation and interpolation registers. t he next stage is a fifth order cascaded integrator comb (cic5) f ilter whose response is defined by the decimation rate. the pu rpose of these filters is to reduce the data rate to the final filter stage so it can calculate more taps per output. the final stage is a sum-of-products fir filter with program- mable 20-bit coefficients, and decimation rates programmable from 1 to 256 (1e32 in practice). the ram coefficient fir filter (rcf in the functional block diagram) can handle a maximum of 160 taps. the overall filter response for the ad6624 is the composite of all decimating and interpolating stages. each successive filter stage is capable of narrower transition bandw idths but requires a greater number of clk cycles to calculate the output. more decimation in the first filter stage will minimize overall power consumption. data from the chip is interfaced to the dsp via a high-speed synchronous serial port. fi gure 18a illustrates the basic function of the ad6624: to select and filter a single channel from a wide input spectrum. t he fre quency translator tunes the desired carrier to baseband. f igure 18b shows the combined filter response of the rcic2, cic5, and rcf. signal of interest e f s /2 wideband input spectrum (e f samp /2 to f samp /2) signal of interest image e3 f s /8 e5 f s /16 e f s /4 e3 f s /16 e f s /8 e f s /16 dc f s /16 f s /8 3 f s /16 f s /4 5 f s /16 3 f s /8 f s /2 wideband input spectrum (e.g., 30mhz from high-speed adc) after frequency translation nco tunes signal to baseband frequency translation (e.g., single 1mhz channel tuned to baseband) e f s /2 e3 f s /8 e5 f s /16 e f s /4 e3 f s /16 e f s /8 e f s /16 dc f s /16 f s /8 3 f s /16 f s /4 5 f s /16 3 f s /8 f s /2 figure 18a. frequency translation of wideband input spectrum khz 10 e1000 1000 dbc e800 e600 e400 e200 0 200 400 600 800 0 e50 e20 e40 e10 e30 e60 0 e80 e100 e70 e90 e110 e120 e140 e130 e150 figure 18b. composite filter response of rcic2, cic5, and rcf
rev. b ad6624 e14e example filter response khz 10 e1000 1000 dbc e800 e600 e400 e200 0 200 400 600 800 0 e50 e20 e40 e10 e30 e60 0 e80 e100 e70 e90 e110 e120 e140 e130 e150 figure 19. filter response th e filter in figure 19 is based on a 65 msps input data rate and an output rate of 541.6666 ksps (two samples per symbol for edge). total decimation rate is 120 distributed between the rcic2, cic5, and rcf. khz 10 dbc e500 e400 e200 0 200 400 500 0 e50 e20 e40 e10 e30 e60 0 e80 e100 e70 e90 e110 e120 e140 e130 e150 figure 20. filter response the filter in figure 20 is designed to meet the is-136 specifica- tions. for this configuration, the clock is set to 61.44 msps with a total decimation rate of 320 providing an output data rate of 192 ksps or four samples per symbol. input data ports the ad6624 features dual, high speed adc input ports, input p ort a and input port b. the dual input ports allow for the most flexibility with a single tuner chip. these can be diversity i nputs or truly independent inputs such as separate antenna segments. either adc port can be routed to one of four tuner channels. for added flexibility, each input port can be used to support multiplexed inputs such as those found on the ad6600 or other adcs with muxed outputs. this added flexibility can allow for up to four different analog sources to be pro- cessed sim ultaneously by the four internal channels. in addition, the front end of the ad6624 contains circuitry that enables high speed signal level detection and control. this is accomplished with a unique high speed level detection circuit that offers minimal latency and maximum flexibility to control up to four analog signal paths. the overall signal path latency from input to output on the ad6624 can be expressed in high- speed clock cycles. the equation below can be used to calculate the latency. t latency = m rc1c2 ( m cic5 + 7) + n taps = 4( sdiv + 1) +18 m rc1c2 and m cic5 are decimation values for the rc1c2 and cic5 filters, respectively, n taps is the number rcf taps cho- sen, and sdiv is the chosen sclk divisor factor. input data format each input port consists of a 14-bit mantissa and 3-bit exponent. if interfacing to a standard adc is required, the exponent bits can be grounded. if connected to a floating point adc such as the ad6600, the exponent bits from that product can be connected to the input exponent bits of the ad6624. the mantissa data format is twos complement and the exponent is unsigned binary. input timing t he data from each high speed input port is latched on the rising edge of clk. this clock signal is used to sample the input port and clock the synchronous signal processing stages that follow in the selected channels. clk in[13:0] exp[2:0] data t si t hi figure 21. input data timing requirements t he clock signals can operate up to 80 mhz and have a 50% duty cycle. in applications using high-speed adcs, the adc sample clock or data valid strobe is typically used to clock the ad6624. clk t clk t clkh t clkl figure 22. clk timing requirements input enable control t here is an iena and an ienb pin for the input port a and input port b, respectively. there are four modes of operation used for each ien pin. using these modes, it is possible to e mulate oper ation of the other rsps such as the ad 6620, which o ffer dual channel modes normally associated with diversity o perations. these modes are: ien transition to low, ien transi- tion to high, ien high, and blank on ien low. in the ien high mode, the inputs and normal operations occur when the input enable is high. in the ien transition to low mode, normal operations occur on the first rising edge of the clock after the ien transitions to low. likewise, in the ien transition to high mode, operations occur on the rising edge of the clock after the ien transitions to high. see the numerically controlled oscillator section for more details on configuring the input enable modes. in blank on ien low mode, the input data is interpreted as zero when ien is low.
rev. b ad6624 e15e a typical application for this feature would be to take the data from an ad6600 diversity adc to one of the inputs of the ad6624. the a/b_out from that chip would be tied to the ien . one channel within the ad6624 would be then set so that i en transition to low is enabled. another channel would be configured so that ien transition to high is enabled. one of the serial outputs would be configured as the serial bus master and the other as a serial bus slave and the output bus configured as shown in figure 25. this would allow two of the ad6624 chan- nels to be configured to emulate that ad6620 in diversity mode. of course the nco frequencies and other channel characteris- tics would need to be set similarly, but this feature allows the ad6624 to handle interleaved data streams such as found on the ad6600. the difference between the ien transition to high and the ien high is found when a system clock is provided that is higher than the data rate of the converter. it is often advantageous to supply a clock that runs faster than the data rate so that additional filter taps can be computed. this naturally provides better filtering. in order to ensure that other parts of the circuit properly recog- nize the faster clock in the simplest manner, the ien transition to low or high should be used. in this mode, only the first clock edge that meets the setup and hold times will be used to latch and process the input data. all other clock pulses are ignored by front end processing. however, each clock cycle will still pro- duce a new filter computation pair. gain switching the ad6624 includes circuitry that is useful in applications where either large dynamic ranges exist or where gain ranging c onverters are employed. this circuitry allows digital thresh- olds to be set such that an upper and a lower threshold can be programmed. one such use of this may be to detect when an adc converter is about to reach full-scale with a particular input condition. the results would be to provide a flag that could be used to q uickly insert an attenuator that would prevent adc overdrive. if 18 db (or any arbitrary value) of attenuation (or gain) is switched in, the signal dynamic range of the system will have been increased by 18 db. the process begins when the input signal reac hes the upper programmed threshold. in a typical application, this may be set 1 db (user-definable) below full- scale. when this input condition is met, the appropriate li (lia-a, lia-b, lib-a, or lib-b) signal associated with either the a or b input port is made active. this can be used to switch the gain or attenuation of the external circuit. the li signal stays a ctive until the input condition falls below the lower programmed threshold. in order to provide hysteresis, a dwell-time register (see memory map for input control registers) is available to hold off switching of the control line for a predetermined num- ber of clocks. once the input condition is below the lower threshold, the programmable counter begins counting high- speed clocks. as long as the input signal stays below the lower t hreshold for the number of high speed clock cycles programmed, the attenuator will be removed on the terminal count. however, if the input condition goes above the lower threshold with the counter running, it will be reset and must fall below the lower threshold again to initiate the process. this will prevent unnec- essary switching between states. t his is illustrated in figure 23. when the input signal goes above the upper threshold, the appropriate li signal becomes active. once the signal falls below the lower threshold, the counter begins counting. if the input condition goes above the lower threshold, the counter is reset and starts again as shown in figure 23. once the counter has terminated to zero, the li signal goes inactive. high dw ell time low time upper threshold lower threshold counter restarts figure 23. threshold settings for li the li signal can be used for a variety of functions. it can be used to set the controls of an attenuator dvga or integrated and used with an analog vga. to simplify the use of this feature, the ad6624 includes two separate gain settings, one when this line is inactive (rcic2_quiet[4:0]) and the other when active (rcic2_loud[4:0]). this allows the digital gain to be adjusted to the external changes. in conjunction with the gain setting, a variable hold-off is included to compensate for the pipeline delay of th e adc and the switching time of the gain control element. together, these two features provide seamless gain switching. another use of these pins is to facilitate a gain range hold-off within a gain-ranging adc. for converters that use gain ranging to incr ease total signal dynamic range, it may be desirable to pro- hibit internal gain ranging from occurring in some instances. for such converters, the li (a or b) signals can be used to hold this off. for this application, the upper threshold would be set based on similar criteria. however, the lower threshold would be set to a level consistent with the gain ranges of the specific converter. the hold-off delay can then be set appropriately for any number of factors such as fading profile, signal peak to average ratio, or any other time-based characteristics that might cause unnecessary gain changes. since the ad6624 has a total of four gain control circuits that can be used if both a and b input ports have interleaved data, each respective li pin is independent and can be set to different set points. it should be noted that the gain control circuits are wideband and are implemented prior to any filtering elements to minimize loop delay. any of the four channels can be set to moni- tor any of the possible four input channels (two in normal mode and four when the inputs are time-multiplexed). the chip also provides appropriate scaling of the internal data based on the attenuation associated with the li signal. in this m anner, data to the dsp maintains a correct scale value th rough- ou t the process, making it totally independent. since finite delays are often associated with external gain switching compo- nents, the ad6624 includes a variable pipeline delay that can be used to compensate for external pipeline delays or gross settling times associated with gain/attenuator devices. this delay may be set up to seven high speed clocks. these features ensure smooth switching between gain settings.
rev. b ad6624 e16e the rssi output of the ad6600 numerically grows with i nc rea s ing signal strength of the analog input (rssi = 5 for a large signal, rssi = 0 for a small signal). when the exponent invert bit (expinv) is set to zero, the ad6624 will consider the smallest signal at the in[13:0] to be the largest and as the exp word increases, it shifts the data down internally (exp = 5 will shift a 14-bit word right by five internal bits before passing the data to the rcic2). in this example, where expinv = 0, the ad6624 regards the largest signal possible on the ad6600 as the smallest signal. thus, the exponent invert b it can be used to make the ad6624 exponent agree with the ad6600 rssi. by setting expinv = 1, it forces the ad6624 to shift the data up (left) for growing exp instead of down. the exponent invert bit should always be set high for use with the ad6600. the exponent offset is used to shift the data right. for example, table i shows that with no rcic2 scaling, 12 db of range is lost when the adc input is at the largest level. this is undesirable because it lowers the dynamic range and snr of the system by reducing the signal of interest relative to the quantization noise floor. table i. ad6600 transfer function with ad6624 expinv = 1, and no expoff adc input ad6600 ad6624 signal level rssi[2:0] data reduction largest 101 (5) 4 (>> 2) e12 db 100 (4) 8 (>> 3) e18 db 011 (3) 16 (>> 4) e24 db 010 (2) 32 (>> 5) e30 db 001 (1) 64 (>> 6) e36 db smallest 000 (0) 128 (>> 7) e42 db (expinv = 1, expoff = 0) to avoid this automatic attenuation of the full-scale adc signal, the expoff is used to move the largest signal (rssi = 5) up to the point where there is no downshift. in other words, once the exponent invert bit has been set, the exponent offset should be adjusted so that mod(7e5 + expoff,8) = 0. this is the case when exponent offset is set to 6 since mod(8,8) = 0. table ii illustrates the use of expinv and expoff when used with the ad6600 adc. table ii. ad6600 transfer function with ad6624 expinv = 1, and expoff = 6 adc input ad6600 ad6624 signal level rssi[2:0] data reduction largest 101 (5) 1 (>> 0) e0 db 100 (4) 2 (>> 1) e6 db 011 (3) 4 (>> 2) e12 db 010 (2) 8 (>> 3) e18 db 001 (1) 16 (>> 4) e24 db smallest 000 (0) 32 (>> 5) e30 db (expinv = 1, expoff = 6) t his flexibility in handling the exponent allows the ad6624 to interface with gain-ranging adcs other than the ad6600. the exponent offset can be adjusted to allow up to seven rssi(exp) ranges to be used as opposed to the ad6600?s five. input data scaling the ad6624 has two data input ports: an a input port and a b input port. each accepts 14-bit mantissa ( twos complement i nteger ) in[13:0], a 3-bit exponent ( unsigned integer ) exp[2:0] and the input enable (ien). both inputs are clocked by clk. these pins allow direct interfacing to both standard fixed-point adcs such as the ad9225 and ad6640, as well as to gain- ranging adcs such as the ad6600. for normal operation with adcs having fewer than 14 bits, the active bits should be msb- justified and the unused lsbs should be tied low. the 3-bit exponent, exp[2:0], is interpreted as an unsigned integer. the exponent will subsequently be modified by either of the 5-bit scale values stored in register 0x92, bits 4? or bits 9?. these 5-bit registers contain the sum of the rcic2 scale value plus the external attenuator scale settings and the exponent offset (expoff). if no external attenuator is used, these values can only be set to the value of the rcic2 scale. if an external attenuator is used, bit position 4? (register 0x92 rc ic2_loud[4:0]) con- tains the scale value for the largest input range. bit positions 9? (register 0x92 rcic2_quiet[4:0]) are used for the nonat- tenu ated input signal range. scaling with fixed-point adcs for fixed-point adcs, the ad6624 exponent inputs exp[2:0] are typically not used and should be tied low. the adc outputs are tied directly to the ad6624 inputs, msb-justified. the expoff bits in 0x92 should be programmed to 0. likewise, the exponent invert bit should be 0. thus for fixed-point adcs, the exponents are typically static and no input scaling is used in the ad6624. d11 (msb) ad6640 d0 (lsb) ad6624 in13 in2 in1 in0 ien exp2 exp1 exp0 vdd expoff = 0, expinv = 0 figure 24. typical interconnection of the ad6640 fixed point adc and the ad6624 scaling with floating-point or gain-ranging adcs an example of the exponent control feature combines the ad 6600 and the ad6624. the ad6600 is an 11-bit adc with three bits of gain ranging. in effect, the 11-bit adc provides the mantissa, and the three bits of relative signal strength indicator (rssi) for the exponent. only five of the eight available steps are used by the ad6600. see the ad6600 data sheet for additional details. for gain-ranging adcs such as the ad6600, scaled input in expinv expweight exp rcic _,, mod( , ) = = = + () in is the value of in[13:0], exp is the value of exp [2:0], and rcic2 is the rcic scale register value (0x92 bits 9? and 40).
rev. b ad6624 e17e it also allows the ad6624 to be tailored in a system that employs the ad6600, but does not utilize all of its signal range. for example, if only the first four rssi ranges are expected to occur, the expoff could be adjusted to five, which would then make rssi = 4 correspond to the 0 db point of the ad6624. d10 (msb) ad6600 d0 (lsb) ad6624 in13 in2 in1 in0 ien exp2 exp1 exp0 rssi2 rssi1 rssi0 ab_out figure 25. typical interconnection of the ad6600 gain- ranging adc and the ad6624 numerically controlled oscillator frequency translation this processing stage comprises a digital tuner consisting of two multipliers and a 32-bit complex nco. each channel of the a d6624 has an independent nco. the nco serves as a quadra- ture local oscillator capable of producing an nco frequency between e clk/2 and +clk/2 with a resolution of clk/2 32 in t he complex mode. the worst-case spurious signal from the nco is better than e100 dbc for all output frequencies. the nco frequency value in registers 0x85 and 0x86 are inter- preted as a 32-bit unsigned integer. the nco frequency is calculated using the equation below. nco freq f clk channel _mod = ? ? ? ? ? ? () nco _ freq is the 32-bit integer (registers 0x85 and 0x86), f channel is the desired channel frequency, and clk * is the ad6624 master clock rate (clk). * see nco mode control section. nco frequency hold-off register when the nco frequency registers are written, data is actually pas sed to a shadow register. data may be moved to the main registers by one of two methods. the first is to start the chip using the soft sync feature, which will directly load the nco registers. the second allows changes to be pre-written and then upd ated through direct software control. to accomplish this, there is an nco frequency hold-off counter. the counter (0x84) is a 16-bit unsigned integer and is clocked at the master clk rate. this hold-off counter is also used in conjunction with the frequency hopping feature of this chip. phase offset the phase offset register (0x87) adds an offset to the phase a ccumulator of the nco. this is a 16-bit register and is inter- preted as a 16-bit unsigned integer. a 0x0000 in this register corresponds to a 0 radian offset and a 0xffff corresponds to an offset of 2 (( )) () ()
rev. b ad6624 e18e lowered, input data is replaced with zero values. during this period, the nco continues to run such that when the ien line is raised again, the nco value will be at the value it would have otherwise been in had the ien line never been lowered. this mode has the effect of blanking the digital inputs when the ien line is lowered. back end processing (rcic2, cic5, and rcf) continues while the ien line is high. this mode is useful for time division multiplexed applications. mode 01: clock on ien high in this mode, data is clocked into the chip while the ien line is high. during the period of time when the ien line is high, new data is strobed on each rising edge of the input clock. when ien line is lowered, input data is no longer latched into the channel. additionally, nco advances are halted. however, back end processing (rcic2, cic5, and rcf) continues during this period. the primary use for this mode is to allow for a clock that is faster than the input sample data rate to allow more filter taps to be computed than would otherwise be possible. in fig- u re 26, input data is strobed only during the period of time when ien is high, despite the fact that the clk continues to run at a rate four times faster than the data. clk t hi t si n+1 n in[13:0] e[2:0] ien figure 26. fractional rate input timing (4 ) () () ( ) () () r l m r rcic rcic 2 2 1 = () l/m must be less than or eq ual to one. this implies that the rcic 2 decimates by 1 or more. resampling is implemented by apparently increasing the input sample rate by the factor l, using zero stuffing for the new data samples. following the resampler is a second order cascaded integrator comb filter. filter characteristics are determined only by the fractional rate change (l/m). the filter can process signals at the f ull rate of the input port, 80 mhz. the output rate of this stage is given by equation 4. f lf m samp rcic samp rcic 2 2 2 = () l rcic 2 and m rcic 2 are unsigned integers. the interpolation rate ( l rcic 2 ) may be from 1 to 512 and the decimation ( m rcic 2 ) may be between 1 and 4096. the stage can be bypassed by setting the decimation to 1/1. the frequency response of the rcic2 filter is given by equation 5. hz l z z hf l mf lf f f s rcic m l s rcic rcic rcic samp samp rcic rcic rcic rcic () () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () s rcic 2 is a programmable, unsigned 5-bit value between 0 and 31. this serves as an attenuator that can reduce the gain of the rcic2 in 6 db increments. for the best dynamic range, s rcic2 should be set to the smallest value possible (i.e., lo west attenuation) without creating an overflow condition. this can be safely accomplished using the following equation:
rev. b ad6624 e19e where input_level is the largest fraction of full-scale possible at the input to the ad6624 (normally 1). the rcic2 scale factor is always used whether or not the rcic2 is bypassed. moreover, there are two scale registers (rcic2_loud[4:0] bits 4? in x92), and (rcic2_quiet[4:0] bits 9? in 0x92) that are used in conjunction with the computed s rcic2 which deter mines the overall rcic2 scaling. the s rcic2 value must be summed w ith the values in each respective scale register and expoff, to determine the scale value that must be placed in the rcic2 scale register. this number must be less than 32 or the interpolation and decimation rates must be adjusted to validate this equation. the ceil function denotes the next whole integer and the floor function denotes the previous whole integer. for example, the ceil(4.5) is 5 while the floor(4.5) is 4. the gain and passband droop of the rcic2 should be calculated by the equations above, as well as the filter transfer equations that follow. excessive passband droop can be compensated for in the rcf stage by peaking the passband by the inverse of the roll-off. scaled input in expinv scaled input in expinv exp rcic exp rcic _, _, mod( , ) mod( , ) = = = = ?+ ??+ () in is the value of in[15:0], exp is the value of exp[2:0], and rcic 2 is the value of the 0x92 (rcic2_quiet[4:0] and rcic2_loud[4:0]) scale register. rcic2 rejection table iii illustrates the amount of bandwidth in percent of the d ata rate into the rcic2 stage. the data in this table may be scaled to any other allowable sample rate up to 80 mhz in single channel mode or 40 mhz in diversity channel mode. the table can be used as a tool to decide how to distribute the decimation between rcic2, cic5, and the rcf. table iii. ssb rcic2 alias rejection table (f samp = 1) bandwidth shown in percentage of f samp m cic5 / l rcic2 ?0 db ?0 db ?0 db ?0 db ?0 db ?00 db 21 .79 1.007 0.566 0.318 0.179 0.101 3 1.508 0.858 0.486 0.274 0.155 0.087 4 1.217 0.696 0.395 0.223 0.126 0.071 5 1.006 0.577 0.328 0.186 0.105 0.059 6 0.853 0.49 0.279 0.158 0.089 0.05 7 0.739 0.425 0.242 0.137 0.077 0.044 8 0.651 0.374 0.213 0.121 0.068 0.038 9 0.581 0.334 0.19 0.108 0.061 0.034 10 0.525 0.302 0.172 0.097 0.055 0.031 11 0.478 0.275 0.157 0.089 0.05 0.028 12 0.439 0.253 0.144 0.082 0.046 0.026 13 0.406 0.234 0.133 0.075 0.043 0.024 14 0.378 0.217 0.124 0.07 0.04 0.022 15 0.353 0.203 0.116 0.066 0.037 0.021 16 0.331 0.19 0.109 0.061 0.035 0.02 example calculations goal: implement a filter with an input sample rate of 10 mhz requiring 100 db of alias rejection for a bw khz mhz fraction = = () ( ) ( ) () () s ceil m floor m l ml floor m l ol m l input level rcic rcic rcic rcic rcic rcic rcic rcic cic rcic rcic s rcic 222 2 2 22 2 2 2 2 2 2 21 2 2 =+ ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = () ()
rev. b ad6624 e20e bit 11 of this register is used to invert the external exponent before internal calculation. this bit should be set high for gain-ranging adcs that use an increasing exponent to represent an increasing signal level. this bit should be set low for gain- ranging adcs that use a decreasing exponent for representing an increasing signal level. in applications that do not require the features of the rcic2, it may be bypassed by setting the l/m ratio to 1/1. this effectively bypasses all circuitry of the rcic2 except the scaling, w hich is still effectual. fifth order cascaded integrator comb filter the third signal processing stage, cic5, implements a sharper, fixed-coefficient, decimating filter than cic2. the input rate to this filter is f samp2 . the maximum input rate is given by equa- tion 9. n ch equals two for diversity channel real input mode; o therwise n ch equals one. in order to satisfy this equation, m cic2 can be increased, n ch can be reduced, or f clk can be increased (refe rence fractional rate input timing described in the input timing section). f f n samp clk ch 2 () () hz z z s m cic cic () = ? ? ? ? ? ? + () hf mf f f f s cic samp samp cic () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + s cic 5 is a programmable unsigned integer between 0 and 20. it serves to control the attenuation of the data into the cic5 stage in 6 db increments. for the best dynamic range, s cic5 should be set to the smallest value possible (lowest attenuation) without creating an overflow condition. this can be safely accomplished using equation 11, where ol r cic2 is the largest fraction of full scale possible at the input to this filter stage. this value is output from the rcic2 stage, then pipelined into the cic5. s ceil m ol ol m ol cic cic rcic cic cic s rcic cic 525 5 2 5 5 5 5 2 5 2 5 = () = () + ( ) () f f m samp samp cic 5 2 5 () ( =) ()
rev. b ad6624 e21e i in q in 160 20b i-ram i out 256 20b c-ram 160 20b q-ram q out figure 27. ram coefficient filter block diagram rcf decimation register each rcf channel can be used to decimate the data rate. the decimation register is an 8-bit register and can decimate from 1 to 256. the rcf decimation is stored in 0xa0 in the form of m rcf -1. the input rate to the rcf is f samp5 . rcf decimation phase the rcf decimation phase can be used to synchronize multiple filters within a chip. this is useful when using multiple channels within the ad6624 to implement polyphase filter allowing the resources of several filters to be operated in parallel and shared. in such an application, two rcf filters would be processing the same data from the cic5. however, each filter will be delayed by one-half the d ecimation rate, thus creating a 180 n taps , is given by the equation below. the value n taps ? is written to the channel register within the ad6624 at address 0xa2. n fm f taps clk rcf samp ? ? ? ? ? ? min 5 160 , (13) the rcf coefficients are located in addresses 0x00 to 0x7f and are interpreted as 20-bit two?-complement numbers. when writing the coefficient ram, the lower addresses will be mul- tiplied by relatively older data from the cic5, and the higher coefficient addresses will be multiplied by relatively newer data from the cic5. the coefficients need not be symmetric and the coefficient length, n taps , may be even or odd. if the coefficients are symmetric, both sides of the impulse response must be writ- ten into the coefficient ram. although the base memory for coefficients is only 128 words long, the actual length is 256 words. there are two pages, each of 128 words. the page is selected by bit 8 of 0xa4. although this data must be written in pages, the internal core handles filters that exceed the length of 128 taps. therefore, the full length of the data ram may be used as the filter length (160 taps). the rcf stores the data from the cic5 into a 160 () + () () () () ( ) () () f f m sampr samp rcf = () + ( )+ + + ()
rev. b ad6624 e22e bit 8 is the rcf bank select bit used to program the register. when this bit is 0, the lowest block of 128 is selected (taps 0 through 127). when high, the highest block is selected (taps 128 through 255). it should be noted that while the chip is computing filters, tap 127 is adjacent to 128 and there are no paging issues. bit 9 selects the origin of the input to each rcf. if bit 9 is cle ar, the rcf input comes from the cic5 normally associ- ated with the rcf. if, however, the bit is set, the input comes from cic5 channel 1. the only exception is channel 1, which uses the output of cic5 channel 0 as its alternate. using this feature, each rcf can either operate on its own channel data or be paired with the rcf of channel 1. the rcf of channel 1 can also be paired with channel 0. this control bit is used with polyphase distributed filtering. if bit 10 is clear, the ad6624 channel operates in normal mode. however, if bit 10 is set, the rcf is bypassed to channel bist. see bist (built-in self-test) section below for more details. user-configurable built-in self-test (bist) the ad6624 includes two built-in test features to test the integ- rity of each channel. the first is a ram bist, w hich is inte nded to test the integrity of the high-speed random access memory within the ad6624. the second is channel bist, which is designed to test the integrity of the main signal paths of the ad6624. each bist function is independent of the other, meaning that each channel can be tested independently at the same time. ram bist th e ram bist can be used to validate functionality of the on-chip ram. this feature provides a simple pass/fail test, which will give confidence that the channel ram is operational. the following steps should be followed to perform this test. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ()( ) ()
rev. b ad6624 e23e micro register i0 i31 q0 q31 shadow register i0 i31 q0 q31 nco frequency register i0 i31 q0 q31 from microport nco frequency update hold-off counter b0 b15 tc ad6624 clk soft sync enable pin sync enable to nco enb figure 28. nco shadow register and hold-off counter start start refers to the start-up of an individual c hannel, chip, or multiple chips. if a channel is not used, it should be put in the sleep mode to reduce power dissipation. following a hard reset (low pulse on the ad6624 reset ), sc start with no sync if no synchronization is needed to start multiple channels or multiple ad6624s, the following method should be used to initialize the device. 1. to program a channel, it should first be set to sleep mode (bit high) (ext address 3). all appropriate control and memo ry registers (filter) are then loaded. the start update hold-off counter (0x83) should be set to 1. 2. set the appropriate sleep bit low (ext address 3). this enables the channel. the channel must have sleep mode low to acti vate a channel. start with soft sync th e ad6624 includes the ability to synchronize channels or chips under microprocessor control. one action to synchronize is the start of channels or chips. the start update hold-off counter (0x83), in conjunction with the start bit and sync bit (ext address 5), allows this synchronization. basically, the start update hold-off counter delays the start of a channel(s) by its value (number of ad6624 clks). the following method is used to synchronize the start of multiple channels via micro- processor control. 1. set the appropriate channels to sleep mode (a hard reset to the ad6624 reset pin brings all four channels up in sleep mode). 2. note that the time rdy (pin 57) goes high to when the nco begins processing data is the contents of the start update hold-off counter(s) (0x83) plus six master clock cycles. 3. write the start update hold-off counter(s) (0x83) to the appropriate value (greater than 1 and less than 2 16e1 ). if the chip(s) is not initialized, all other registers should be loaded at this step. 4. w rite the start bit and the sync bit high (ext address 5). 5. this starts the start update hold-off counter counting down. the counter is clocked with the ad6624 clk signal. when it reaches a count of one, the sleep bit of the appropri- ate channel(s) is set low to activate the channel(s). start with pin sync t he ad 6624 has four sync pins, a, b, c, and d, that can be used to provide for very accurate synchronization channels. each channel can be programmed to look at any of the four sync pins. additionally, any or all channels can monitor a single sync p in or each can monitor a separate pin, providing complete flexibil- ity of s ynchronization. synchronization of start with one of the e xternal signals is accomplished with the following method. 1. s et the appropriate channels to sleep mode (a hard reset to the ad6624 reset s) sc c sc()() wsc()() ( ) (), ssss e(ea)(a,,c,d) wsadck, s ctadck w,s ()() cc t (ss)s (s) tc, set freq no hop 1. set the nco freq hold-off counter to 0. 2. load the appropriate nco frequency. the new frequency will be immediately loaded to the nco. hop with soft sync the ad6624 includes the ability to synchronize a change in nco frequency of multiple channels or chips under micropro- cessor control. the nco freq hold-off counter (0x84), in conjunction with the hop bit and the sync bit (ext address 4), allow this synchronization. basically, the nco freq hold-off counter delays the new frequency from being loaded into the nco by its value (number of ad6624 clks). the following method is used to synchronize a hop in frequency of multiple channels via microprocessor control.
rev. b ad6624 e24e 1. note that the time from when rdy (pin 57) goes high to when the nco begins processing data is the contents of the nco freq hold-off counter (0x84) plus seven master clock cycles. 2. write the nco freq hold-off (0x84) counter to the appro- priate value (greater than 1 and less then 2 16e1 ). 3. write the nco frequency register(s) to the new desired frequency. 4. write the hop bit and the sync(s) bit high (ext address 4). 5. this starts the nco freq hold-off counter counting down. the counter is clocked with the ad6624 clk signal. when it reaches a count of one, the new frequency is loaded into the nco. hop with pin sync the ad6624 includes four sync pins to provide the most accu- rate synchronization, especially between multiple ad6624s. synchronization of hopping to a new nco frequency with an external signal is accomplished using the following method: 1. note that the time from when the sync pin goes high to when the nco begins processing data is the contents of the nco freq hold-off counter (0x84) plus five master clock cycles. 2. write the nco freq hold-off counter(s) (0x84) to the appropriate value (greater than 1 and less than 2 16e1 ). 3. write the nco frequency register(s) to the new desired frequency. 4. set the hop on pin sync bit and the appropriate sync pin enable high. 5. when the selected sync pin is sampled high by the ad6624 clk, it enables the count-down of the nco freq hold-off c ounter. the counter is clocked with the ad6624 clk signal. when it reaches a count of one, the new frequency is loaded into the nco. serial output data port t he ad6624 has four configurable serial output ports (sdo0, sd o1, sdo2, and sdo3). each port can be operated inde- pendently of the other, making it possible to connect each to a different dsp. in the case where a single dsp is required, the ports can easily be configured to work with a single serial port on a single dsp. as such, each output may be configu red as either serial master or slave. additionally, each channel can be configured independently of the others. serial output data format the ad6624 works with a variety of output data formats. these include word lengths of 12-, 16-, and 24-bit precision. in addi- tion to the normal linear binary data format, the ad6624 offers a floating-point data format to simplify numeric processing. these formats are 8-bit mantissa with 4-bit exponent, and 12-bit m antissa and 4-bit exponent. these modes are available re gardless of the bit precision of the serial data frame. in the normal linear binary data format, a programmable internal 4-bit scaling fa ctor is used to scale the output. see the rcf output scale factor section and c ontrol register above for more details. in all modes, the data is shifted out of the device in big endian format (msb first). in floating-point mode, the chip normally determines the expo- nent automatically; however, the chip can be forced to use the same exponent for both the real and imaginary portion of the data. the choice of exponents favors prevention of numerical overflow at the expense of small number accuracy. however, this should not be a problem as small numbers imply numbers close to zero. finally, the ad6624 channel can be forced to use a preselected scale factor if desired. this allows for a consistent range of data useful to many applications. serial data frame (serial bus master) the serial data frame is initiated with the serial data frame sync (sd fs 0, sdfs1, sdfs2, or sdfs3). as e ach channel within the ad6624 completes a filter cycle, data is transferred into the serial data buffer. in the serial bus master (sbm) mode, the inter- na l serial controller initiates the sdfs on the next rising edge of the serial clock. in the ad6624, there are three different modes in which the frame sync may be generated as a serial bus master. in the first mode, the sdfs is valid for one complete clock cycle prior to the data shift. on the next clock cycle, the ad6624 begins shifting out the digitally processed data stream. depending on the bit precision of the serial configuration, either 12, 16, or 24 bits of i data are shifted out, followed by 12, 16, or 24 bits of q data. the format of this data will be in one of the formats listed above. in the second mode, the sdfs is high for the entire time that valid bits are being shifted. the sdfs bit goes high concurrent with the first bit shifted out of the ad6624. 24 16 12 i[23:12] i[23:12] i[23:12] i[1:8] i[1:8] q[23:20] i[7:0] q[23:2] q[19:8] q[23:2] q[11:8] z, new-i q[7:0] z, new-i z, new-i sclk sdfs sdfe sdo 12345678 9 10 123456789 20 12 345 678 9 30 123456789 40 12 3 456 789 figure 29. sdfs valid for one sclk cycle 24 16 12 i[23:12] i[23:13] i[23:12] i[1:8] i[1:8] q[23:20] i[7:0] q[23:2] q[19:8] q[23:2] q[11:8] z, new-i q[7:0] z, new-i z, new-i sclk sdfs sdfe sdo 12345678 9 10 123456789 20 12 345 6789 30 123456789 40 12 3 4 567 8 9 figure 30. sdfs is high during data shift in the final mode, the sdfs bit goes high as in the first mode, one clock cycle prior to the actual data. however, a second sdfs is inserted one clock cycle prior to the shift of the first q bit. in this manner, each word out of the ad6624 is accompanied by an sdfs. sclk 12345678 9 10 123456789 20 12 345 678 9 30 123456789 40 12 3 4 567 8 9 sdfs sdfe sdo 24 16 12 i[23:12] i[23:13] i[23:12] i[1:8] i[1:8] q[23:20] i[7:0] q[23:2] q[19:8] q[23:2] q[11:8] z, new-i q[7:0] z, new-i z, new-i figure 31. a second sdfs inserted prior to first q bit regardless of the mode above, the sdfe behaves the same in each. on the last bit of the serial frame (least significant bit of the q word), the serial data frame end (sdfe) is raised. the sdfe signal can either be used by the dsp to indicate the end
rev. b ad6624 e25e of the frame or it can be used as the sdfs (serial data frame sync) of another ad6624 chip or channel running in serial cascade mode. serial data frame (serial cascade) any of the ad6624 serial outputs may be operated in the serial cascade mode (serial slave). in this mode, the selected ad6624 channel requires an external device such as a dsp to issue the serial clock and sdfs. to operate successfully in the serial cascade mode, the dsp must have some indication that the ad6624 channel?s serial buffer is ready to send data. this is indicated by the assertion of the drx pin where x is the channel number. this pin should be tied to an interrupt or flag pin of the dsp. in this manner, the dsp will know when to service the serial port. when the dsp begins handling the serial service, the serial port should be configured such that the sdfs pin is asserted one clock cycle prior to shifting data. as such, the ad6624 channel samples the sdfs pin on the rising edge of the serial clock. on the next rising edge of the serial clock, the ad6624 serial port begins shifting data until the specified number of bits has been shifted. sclk sdo sdfs i 15 i 14 q 1 q 0 t hsf t ssf figure 32. sdo, sdfs switching characteristics (sbm = 0) on the last bit of the serial frame (least significant bit of the q word), the sdfe is raised. the sdfe signal can either be used by the dsp to indicate the end of the frame or it can be used as the sdfs of another ad6624 chip or channel running in serial cascade mode. sclk sdo sdfe t dsdfe i 15 i 14 q 1 q 0 t dso figure 33. sdo, sdfe switching characteristics configuring the serial ports each serial output port may function as either a master or slave. a serial bus master will provide sclk (sclk0, sclk1, sclk2, sclk3) and sdfs outputs. a serial slave will accept these signals as inputs. upon the lift of reset , s s, ss,, reset t s,s,s a registers high. serial port data rate if a serial port is defined as a master, the sclk frequency is defined by equation 15. f clk is the frequency of the master clock of the ad6624 channel and sdiv is the serial divi sion word for the channel (1, 2, or 3). the sdiv for ser ial port 0 is located directly as pins on the package for easy hardware configuration and is not mapped into 0xa9. for serial p orts 1, 2, and 3, the internal register 0xa9 bits 3? define the sdiv (sdiv0, sdiv1, sdiv2, sdiv3) word. f f sdiv sclk clk = + () () 10k figure 34. typical serial data output interface to dsp (serial master mode, sbm = 1) serial slave operation the ad6624 can also be operated as a serial bus slave. in this configuration, shown in figure 35, the serial clock provided by the dsp can be asynchronous with the ad6624 clock and input data. in this mode, the clock has a maximum frequency of 62.5 mhz and must be fast enough to read the entire serial frame prior to the next fr ame coming available. since the ad6624 output is derived (via the decimation/interpolation rates) from its input sample rate, the output rate can be determined by the user. the output rate of the ad6624 is given below. f fl mmm out adc cic cic cic rcf = ()
rev. b ad6624 e26e sdiv0 sclk dt dr rfs sclk sdi sdo sdfs sdfe sbm0 ad6624 dsp ch 0 4 10k 10k figure 35. typical serial data output interface to dsp (serial slave mode, sbm = 0) serial ports cascaded serial output ports may be cascaded on the ad6624 such that the sdo?s outputs are shorted together. in this mode, the sdo port of the master channel three-states when the sdo port of the slave channel is active. this allows data to be shifted out of a slave channel immediately following the completion of data frame (i/q pair) shifting out of a master ad6624 channel. to accomplish this, the sdfe signal of the master channel drives the sdfs input of the slave channel. serial output port cascad- ing can be used with channels on the same ad6624 device, or with channels on two different devices as shown in figure 36. to satisfy t ssf and t hsf timing requirements of the slave chan- nel, the sdfe signal from the master channel should be delayed using a noninverting buffer (e.g., 74lvc244a) that provides a minimum of 1.5 ns of propagation delay. figure 36 shows the cascade capability between two ad6624 devices. the first is connected as a serial master (sbm = 1) and the second is con- figured in serial cascade mode (sbm = 0). using the ad6624 master/slave mode permits a dsp to shift the data from the master ad6624 serial port, followed immedi- ately by a frame of data (i and q words) from the ad6624 slave p ort. as shown in figure 36, the master port is serial port 0. the slave port can be either serial port 1, 2, or 3, or a serial port 0 fr om another ad6624. other ad6624 serial ports can be cascaded to the slave port by using the sdfe and sdfs in the manner shown. the only limit to the number of ports that can be cas- caded comes from serial bandwidth and fan-out considerations. there must be enough serial clock cycles available to shift the necessary data into the dsp, and the sclk (common to all channels and dsp) must be closely monitored to ensure that it is a clean signal. for systems where a single dsp serial port will be connected to many ad6624 serial ports, it is recommended that the sclk signal from the master be buffered to the slaves. see serial port buffering in the applications section. sdiv0 sclk dt dr rfs sclk sdi sdo sdfs sdfe sbm0 3.3v ad6624 dsp ch 0 master 4 sclk sdi sdo sdfs sdfe ad6624 ch 0 cascade 10k 10k bu ffer figure 36. typical serial data output interface to dsp (serial cascade mode, sbm = 0) serial output frame timing (master and slave) the sdfs signal transitions accordingly depending on whether the part is in master (sbm = 1, figure 43) or slave (sbm = 0, figure 32) mode. the next rising edge of sclk after this occurs will drive the f irst bit of the serial data on the sdo pin. the falling edge of sclk or the subsequent rising edge can then be used by the dsp to sample the data until the required number of bits is received (determined by the serial output port word length). if the dsp has the ability to count bits, the dsp will know when the complete frame is received. if not, the dsp can monitor the sdfe pin to determine that the frame is complete. serial port timing specifications whether the ad6624 serial channel is operated as a serial bus m aster or as a serial slave, the serial port timing is identical. fig ures 38 to 44 indicate the required timing for each of the specifications. sclk t sclkl t sclk t sclkh figure 37. sclk timing requirements clk sclk t dsclkh t sclkh t sclkl figure 38. sclk switching characteristics (divide by 1)
rev. b ad6624 e27e table viii. channel address memory map ch address register bit width comments 00e7f coefficient memory (cmem) 20 128 () () () () + +
rev. b ad6624 e28e table viii. channel address memory map (continued) ch address register bit width comments a5 bist signature for i path 16 bist-i a6 bist signature for q path 16 bist-q a7 # of bist outputs to accumulate 20 19e0: # of outputs (counter value read) a8 ram bist control register 3 2: d-ram fail/pass 1: c-ram fail/pass 0: ram bist enable a9 serial port control register 10 9: map rcf data to bist registers 8e7: i_sdfs control 1x: separate i and q sdfs pulses 01: sdfs high for entire frame 00: single sdfs pulse 6e5: sowl 1x: 24-bit words 01: 16-bit words 00: 12-bit words 4: sbmx 3e0: sdivx[3:0] sclk sdi data t ssi t hsi figure 39. serial input data timing requirements sclk sdo i 15 i 14 t dsdo i 13 figure 40. serial output data switching characteristics sclk sdfs t ssf t hsf figure 41. sdfs timing requirements (sbm = 0) sdo i msb sdfs sclk t dso i msb1 sdfs minimum width is one sclk first data is available the first rising sclk after sdfs goes high figure 42. timing for serial output port (sbm = 1) sclk sdfs sdfe t dsdfs t dsdfe figure 43. ser ial frame switching characteristics (sbm = 1) sclk sdo sdfe t dsdo t dsdfe q 1 q 0 i 14 i 15 figure 44. sdo, sdfe switching characteristics sbm0 sbm0 is the serial bus master pin for the channel 0 serial port only. serial ports 1, 2, and 3 will always default to serial slave mode but can be programmed as masters in the internal register s pace. the sbm0 pin gives the user the option to boot the ad6624 through serial port 0 as a master. when sbm0 is high (master mode), the ad6624 generates sclk0 and sdfs0. when sbm0 is low (slave mode), the ad6624 accepts external sclk0 and sdfs0 signals. when configured as a bus master, th e sclk0 signal can be used to strobe data into the dsp inter- face. when used with another ad6624 in serial cascade m ode, sclk0 can be taken from the master ad6624 and used to shift data out from the cascaded device. in this situation, sdfs of the slave ad6624 channel is connected to the sdfe pin of the master ad6624 channel (or the preceding chip in the chain). when an ad6624 is in serial slave mode, all of the serial port activities are controlled by the external signals sclk and sdfs.
rev. b ad6624 e29e regardless of whether the chip is a serial bus master or is in serial slave mode, the ad6624 serial port functions are identi- cal except for the source of the sclk and sdfs pins. sclk sclk is an output when sbm (sbm0 or register bit for serial ports 1, 2, and 3) is high; sclk is an input when sbm (sbm0 or register bit for serial ports 1, 2, and 3) is low in serial slave mode. in either case, the sdin input is sampled on the falling edge of sclk and all outputs are switched on the rising edge of sclk. the sdfs pin is sampled on the falling edge of sclk. this allows the ad6624 to recognize the sdfs in time to initiate a frame on the very next sclk rising edge. the maximum speed of this port is 80 mhz. sdin sdin is the serial data input. serial data is sampled on the f alling edge of sclk. this pin is used in the serial control mo de to write the internal control registers of the ad6624. these activities are described later in the serial port control section. the serial input port is self-framing and bears no fixed relationship to either sdfs or sdfe. sdo sdo is the serial data output. serial output data is shifted on the ris ing edge of sclk. on the very next sclk rising edge after an sdfs, the msb of the i data from the channel is shifted. on every subsequent sclk edge, a new piece of data is shifted out on the sdo pin until the last bit of data is shifted out. the last bit of data shifted is the lsb of the channel?s q data. sdo is three-stated when the serial port is outside its time-slot. this allows the ad6624 to share the sdin of a dsp with other ad6624s or other devices. sdfs sdfs is the serial data frame sync signal. sdfs is an output w hen sbm (sbm0 or register bit for serial ports 1, 2, and 3) is high in the master mode. sdfs is an input when sbm (sbm0 or register bit for serial ports 1, 2, and 3) is low in the sl a ve mode. sdfs is sampled on the falling edge of sclk. when sbm is sampled low, the ad6624 serial port will func- tion as a serial slave. in this mode, the port is silent until the dsp issues a frame sync. when the ad6624 detects an sdfs on the falling edge of a dsp-generated serial clock, on the next rising edge of the serial clock, the ad6624 enables the output driver and shifts the msb of the i word. data is shifted until the lsb of the q word has been sent. on the lsb of the q word, the ad6624 generates an sdfe, which can be cascaded to the next sdfs on a tdm serial chain or to the dsp to indicate that the last bit has been sent. when sbm is sampled high, the chip functions as a serial bus master. in this mode, the ad6624 is responsible for generating serial control data. three modes of that operation are set via channel address 0xa9 bits 8e7. each behaves a little differently, as detailed below. in the first mode (0xa9 bits 8e7:00), the sdfs is valid for one complete clock cycle prior to the data shift. on the next clock cycle, the ad6624 begins shifting serial data. in the second m ode, (0xa9 bits 8e7:01), the sdfs is high for the entire time that valid bits are being shifted. the sdfs bit goes high co ncurrent with the first bit shifted out of the ad6624 and returns low after the last bit is shifted out of the ad6624. in the third mode (0xa9 bits 8e7:10), the sdfs bit goes high as in the first mode, one clock cycle prior to the actual data. however, a second sdfs is inserted one clock cycle prior to the shift of the first q bit. in this manner, each word out of the ad6624 is accom- panied by an sdfs. sdfe sdfe is the serial data frame end output. sdfe will go high during the last sclk cycle (lsb of the q word) of an active time-slot. the sdfe output of a master ad6624 channel can be tied to the input sdfs of an ad6624 channel in serial slave mode in order to provide a hard-wired time-slot scenario. when t he last bit of sdo data is shifted out of the master ad6624, the sdfe signal will be driven high by the same sclk rising edge on which this bit is clocked out. on the falling edge of this sclk cycle, the slaved serial port will sample its sdfs signal, which is hard-wired to the sdfe of the master. on the very next sclk rising edge, data of the slave will start shifting. there will be no rest between the time slots of the master and slave. serial word length bits 6e5 of register 0xa9 determine the length of the serial word (i or q ). if these bits are set to ?00,? each word is 12 bits (12 bits for i and 12 more bits for q). if set to ?01,? the serial words ar e 16 bits wide, and if set to ?1x? (x is don?t care), the word length is 24 bits. sdfs mode bits 8e7 of register 0xa9 determine how the sfds behaves in serial bus master mode. in serial slave mode, the frame sync must be formatted by programming bits 8e7 to ?00.? the first mode is set by programming bits 8e7 to ?00?. in this mode, the sdfs is valid for one complete clock cycle prior to the data shift. on the next clock cycle, the ad6624 begins shift- ing out the digitally processed data stream. depending on the bit precision of the serial configuration, either 12, 16, or 24 bits of i data are shifted out, followed by 12, 16, or 24 bits of q data. the second mode is set by programming bits 8e7 to ?01.? in this mode, the sdfs is high for the entire time that valid bits are being shifted. the sdfs bit goes high concurrent with the first bit shifted out of the ad6624 and goes low after the last bit has been shifted. the third mode is set by programming bits 8e7 to ?1x? (x is don?t care). in this mode, the sdfs bit goes high as in the first mode, one clock cycle prior to the actual data. however, a sec- ond sdfs is inserted one clock cycle prior to the shift of the first q bit. in this manner, each word out of the ad 6624 is accompa- nied by an sdfs. mapping rcf data to the bist registers if bit 9 of 0xa9 is set, rcf data is routed to the bist registers. this allows the filter results to be read from the mi croprocessor port. this can be useful when the data must be accessed via a p arallel port and the decimation rate is sufficiently high that throughput does not become an issue. 0x00e0x7f: coefficient memory (cmem) this is the coefficient memory (cmem) used by the rcf. it is memory mapped as 128 words by 20 bits. a second 128 words of ram may be accessed via this same location by writing bit 8 of the rcf control register high at channel address 0xa4. the filter calculated will always use the same coefficients for i and q. by using memory from both of these 128 blocks, a filter up to 160 taps can be calculated. mul tiple filters can be l oaded and selected with a single internal access to the coefficient offset register at channel address 0xa3.
rev. b ad6624 e30e 0x80: channel sleep register this register contains the sleep bit for the channel. when this bit is high, the channel is placed in a low power state. when this bit is low, the channel processes data. note that in serial slave mode, the reset sck t seew see, see sscr tsc , c w ,cc ws,s c w,s scr tsc asc t sscs tsc sc ssc sc tsc ss sscsct , see , ada sc adc ,s sc ,sc cc tcc sscsc t ,c t sc,c sc , c ,c w, ac, c sc,a c cr tsc t seesscsc , c c, cr t sc t see sscsc , c c, cr tc bits 8? of this register choose which of the four sync pins are used by the channel. the sync pin selected can be used to initiate a start, hop, or timing adjustment to the channel. the synchronization section of this data sheet provides more details on this. bit 6 of this register defines whether the a or b input port is used by the channel. if this bit is low, the a input port is selected; if this bit is high, the b input port is selected. each input port consi sts of a 14-bit input mantissa (inx[ 13:0]), a 3-bit exponent (ex px[2:0]), and an input enable pin, ienx. the x represents either a or b. b its 5? determine how the sample clock for the channel is derived from the high-speed clk signal. there are four pos- sible choices. each is defined below but for further detail, the nco section of the data sheet should be consulted. when these bits are 00, the input sample rate (f samp ) of the channel is equal to the rate of the high-speed clk signal. when ien is low, the data going into the channel is masked to 0. this is an appropriate mode for tdd systems where the receiver may wish to mask off the transmitted data yet still remain in the proper phase for the next receive burst. when these bits are 01, the input sample rate is determined by the fraction of the rising edges of clk on which the ien i nput is high. for example, if ien toggles on every rising edge of c lk, then the ien signal will only be sampled high on one out of every two rising edges of clk. this means that the input sample rate f samp will be 1/2 the clk rate. when these bits are 10, the input sample rate is determined by the rate at which the ien pin toggles. the data that is captured on the rising edge of clk after ien transitions from low to
rev. b ad6624 e31e high is processed. when these bits are 11, the accumulator and sa mple clk are determined by the rate at which the ien pin toggles. the data that is captured on the rising edge of clk a fter ien transitions from high to low is processed. for example, con trol modes 10 and 11 can be used to allow interleaved data from either the a or b input ports and then assigned to the respec- tiv e channel. the ien pin selects the data such that a channel could be configured in mode 10 and another could be config- ured in mode 11. bit 3 determines whether or not the phase accumulator of the nco is cleared when a hop occurs. the hop can originate from either the pin_sync or soft_sync. when this bit is set to 0, the hop is phase continuous and the accumulator is not cleared. when this bit is set to 1, the accumulator is cleared to 0 before it begins accumulating the new frequency word. this is appropriate when multiple channels are hopping from different frequencies to a common frequency. bits 2? control whether or not the dithers of the nco are acti- vated. the use of these features is heavily determined by the system constraints. consult the nco section of the data sheet for more detailed information on the use of dither. bit 0 of this register allows the nco frequency translation stage to be bypassed. when this occurs, the data from the a input port is passed down the i path of the channel and the data from the b in put port is passed down the q path of the channel. this allows a real filter to be performed on baseband i and q data. 0x90: rcic2 decimation? (m rcic2 ?) this register is used to set the decimation in the rcic2 filter. the value written to this register is the decimation minus one. the r cic2 decimation can range from 1 to 4096 depending upon the interpolation of the channel. the decimation must always be greater than the interpolation. m rcic2 must be chosen larger than l rcic2 and both must be chosen such that a suitable rcic2 s calar can be chosen. for more details, consult the rcic2 section. 0x91: rcic2 interpolation? (l rcic2 ?) this register is used to set the interpolation in the rcic2 filter. the value written to this register is the interpolation minus one. t he rcic2 interpolation can range from 1 to 512 depending upon the decimation of the rcic2. there is no timing error a ssociated with this interpolation. see the rcic2 section of the data sheet for further details. 0x92: rcic2 scale the rcic2 scale register is used to provide attenuation to com- pensate for the gain of the rcic2 and to adjust the linearization of the data from the floating- point input. the use of this scale r egister is influenced by both the rcic2 growth and floating- p oint input port considerations. the rcic2 section should be consulted for details. the rcic2 scalar has been combined with the exponent offset and will need to be handled appropriately in both the input port and rcic2 sections. bit 11 determines the polarity of the exponent. normally, this bit will be cleared unless an adc such as the ad6600 is used, in which case, this bit will be set. bit 10 determines the weight of the exponent word associated with the input port. when this bit is low, each exponent step is considered to be worth 6.02 db. when this bit is high, each exponent step is considered to be worth 12.02 db. bits 95 are the actual scale values used when the level indica- tor, li pin associated with this channel is active. bits 4? are the actual scale values used when the level indica- tor, li pin associated with this channel is inactive. 0x93: reserved. (must be written low.) 0x94: cic5 decimation? (m cic5 ?) this register is used to set the decimation in the cic5 filter. the value written to this register is the decimation minus one. although this is an 8-bit register, the decimation is usually lim- ited to values between 1 and 32. decimations higher than 32 would require more scaling than the cic5? capability. 0x95: cic5 scale the cic5 scale factor is used to compensate for the growth of the cic5 filter. consult the cic5 section for details. 0x96: reserved. (must be written low.) 0xa0: rcf decimation? (m rcf ?) this register is used to set the decimation of the rcf stage. the value written is the decimation minus one. although this is an 8-bit register that allows decimation up to 256 for most filtering sce- narios, the decimation should be limited to values between 1 and 32. higher decimations are allowed, but the alias protection of the rcf may not be acceptable for some applications. 0xa1: rcf decimation phase (p rcf ) this register allows any one of the m rcf phases of the filter to be used and can be adjusted dynamically. each time a filter is started, this phase is updated. when a channel is synchronized, it will retain the phase setting chosen here. this can be used as part of a timing recovery loop with an external processor or can allow multiple rcfs to work together while using a single rcf pair. the rcf section of the data sheet should be consulted for further details. 0xa2: rcf number of taps minus one (n rcf ?) t he number of taps for the rcf filter minus one is written here. 0xa3: rcf coefficient offset (co rcf ) this register is used to specify which section of the 256-word coefficient memory is used for a filter. it can be used to select among multiple filters that are loaded into memory and refer- e nced by this pointer. this register is shadowed and the filter p ointer is updated every time a new filter is started. this allows the coefficient offset to be written even while a filter is being computed with disturbing operation. the next sample that comes out of the rcf will be with the new filter. 0xa4: rcf control register the rcf control register is an 11-bit register that controls general features of the rcf as well as output formatting. the bits of this register and their functions are described below. bit 10 bypasses the rcf filter and sends the cic5 output data to the bist-i and bist-q registers. the 16 msbs of the cic5 data can be accessed from this register if bit 9 of the serial control register at channel address 0xa9 is set. bit 9 of this register controls the source of the input data to the rcf. if this bit is 0, the rcf processes the output data of its own channel. if this bit is 1, it processes the data from the cic5 of another channel. the cic5 that the rcf is connected to when this bit is 1 is shown in table ix. this can be used to allow multiple rcfs to be used together to process w ider bandwidth channels. see the multiprocessing section of the data sheet for further details.
rev. b ad6624 e32e table ix. rcf input configurations channel rcf input source when bit 9 is 1 01 10 21 31 bit 8 is used as an extra address to allow a second block of 128 words of cmem to be addressed by the channel addresses at 0x00?x7f. if this bit is 0, the first 128 words are written and if this bit is 1, a second 128 words is written. this bit is only used to program the coefficient memory. it is not used in any way by the processing and filters longer than 128 taps can be performed. bit 7 is used to help control the output formatting of the ad6624s rcf data. this bit is only used when the 8 + 4 or 12 + 4 floating- point modes are chosen. these modes are enabled by bits 5 and 4 of this register below. when this bit is 0, the i and q output exponents are determined separately based on their i ndividual magnitudes. when this bit is 1, the i and q data is a complex floating-point number where i and q use a single exponent that is determined based on the maximum magnitude of i or q. bit 6 is used to force the output scale factor in bits 3? of this register to be used to scale the data even when one of the float- ing point output modes is used. if the number is too large to represent with the output scale chosen, the mantissas of the i and q data clip and do not overflow. bits 5 and 4 choose the output formatting option used by the rcf data. the options are defined in table x and are dis- cussed further in the output format section of the data sheet. table x. output formats bit values output option 1x 12-bit mantissa and 4-bit exponent (12 + 4) 01 8-bit mantissa and 4-bit exponent (8 + 4) 00 fixed-point mode bits 3? of this register represent the output scale factor of the rcf. they are used to scale the data when the output format is in fixed-point mode or when the force exponent bit is high. 0xa5: bist register for i this register serves two purposes. the first is to allow the com- plete functionality of the i data path in the channel to be tested in the system. the bist section of the data sheet should be consulted for further details. the second function is to provide access to the i output data through the microport. to accom- plish this, the map rcf data to bist bit in the serial port c ontrol register, 0xa9, should be set high. sixteen-bits of i data can then be read through the microport in either the 8 + 4, 12 + 4, 12-bit linear or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa6: bist register for q this register serves two purposes. the first is to allow the com- plete functionality of q data path in the channel to be tested in the system. the bist section of the data sheet should be con- s ulted for further details. the second function is to provide access to the q output data through the microport. to accomplish this, the map rcf data to bist bit in the serial port control regis- ter, 0xa9, should be set high. sixteen bits of q data can then be read through the microport in either the 8 + 4, 12 + 4, 12-bit linear, or 16-bit linear output modes. this data may come from either the formatted rcf output or the cic5 output. 0xa7: bist control register this register controls the number of outputs of the rcf or cic fil ter that are observed when a bist test is performed. the bist signature registers at addresses 0xa5 and 0xa6 will observe this nu mber of outputs and then terminate. the loading of these registers also starts the bist engine running. details of how to utilize the bist circuitry are defined in the bist section of the data sheet. 0xa8: ram bist control register this register is used to test the memories of the ad6624 should they ever be su spected of a failure. bit 0 of this register is written with a one when the channel is in sleep and the user waits for 1600 clks and then polls the bits. if bit 1 is high, the cmem failed the test; if bit 2 is high, the data memory used by the rcf failed the test. 0xa9: serial port control register this register controls the serial port of the ad6624 and, along with the rcf control register, it helps to determine the out- put format. bit 9 of this register allows the rcf or cic5 data to be mapped to the bist registers at addresses 0xa5 and 0xa6. when this bit is 0, the bist register is in signature mode and ready for a self-test to be run. when this bit is 1, the output data from the rcf after formatting or the cic5 data is mapped to these r egisters and can be read through the microport. in addition, when this bit is high, the dr pin for the channel delivers a 1 clk cycle wide pulse that can be used to synchronize the host processor with the ad6624. this signal is a 1 sclk cycle wide pulse when this bit is 0. bits 8 and 7 control the output format of the sdfs pulse. when these bits are 00, there is a single sclk cycle wide pulse for the i and q data. when these bits are 01, the sdfs signal is h igh for all of the bits shifted during the serial frame. when these bits are 10 or 11, there are two sdfs pulses that are each 1 sclk cycle wide. one pulse precedes the i word of data and the second precedes the q word of data. when a serial port is configured as a serial slave, it should be in the first mode with these bits set to 00. bits 6 and 5 determine the serial word length used by the serial port. if these bits are 00, the serial ports use 12-bit words and shift 12 bits of i followed by 12 bits of q with each shifted msb first. if these bits are 01, the serial ports use 16-bit words and shift 16 bits of i followed by 16 bits of q with each shifted msb first. if these bits are 1x, the serial ports use 24-bit words and shift 24 bits of i followed by 24 bits of q with each shifted msb first. when the fixed point output option is chosen from the rcf control register, these bits also set the rounding correctly in the output formatter of the rcf. bit 4 of this register controls whether the serial port is a master or slave. this register powers up low so that the serial port is a slave in order to avoid contention problems on the output driv- ers. the serial port for channel 0 does not use this bit. the master/slave status of serial port 0 is set by the sbm0 pin. bits 3? control the rate of the sclk signal when the channel is master. this four-bit bus can set the sclk as a division of the master clk from 1 to 16 with approximately a 50% duty cycle.
rev. b ad6624 e33e the sclk can be generated and run up to a maximum of 80 mhz. the serial division bits from this register are not used for serial port 0. the external sdiv [3:0] pins are used to determine this for serial port 0. microport control the ad6624 has an 8-bit microprocessor port and four serial input ports. the use of each of these ports is described sepa- rately below. the interaction of the ports is then described. the microport interface is a multimode interface that is designed to give flexibility when dealing with the host processor. there are two modes of bus operation: intel nonmultiplexed mode (inm), a nd motorola nonmultiplexed mode (mnm). the mode is s elected based on host processor and which mode is best suited to that processor. the microport has an 8-bit data bus (d[ 7:0]), 3-bit address bus (a[2:0]), three control pins lines ( cs , ds rd ,rw wr ),( dtack rd)t ,r e tec ast t(t er ca)t scc exactly the same functions, although at a slower rate. access control register (acr) t he access control register serves to define the channel or chan- nels that receive an access from the microport or serial port 0. bit 7 of this register is the autoincrement bit. if this bit is a 1, the car register described below will increment its value after every access to the channel. this allows blocks of address s pace such as coefficient memory to be initialized more efficiently. bit 6 of the register is the broadcast bit and determines how bits 5? are interpreted. if broadcast is 0, bits 5?, which are re ferred to as instruction bits (instruction [3:0]), are com pared with the chip_id [3:0] pins. the instruction that matches the chip_id [3:0] pins will determine the access. this allows up to 16 chips to be connected to the same port and memory mapped without external logic. this also allows the same serial port of a host processor to configure up to 16 chips. if the broadcast bit is high, the instruction [3:0] word allows multiple ad6624 chan- nels and/or chips to be configured simultaneously, inde pendent of the chip_id[3:0] pins. ten possible instructions are defined in table xii. this is useful for smart antenna systems where multiple channels listening to a single antenna or carrier can be si multaneously configured. the x(s) in the table represent ?on? cares?in the digital decoding. table xi. external memory map a[2:0] name comment 111 access control register (acr) 7: auto increment 6: broadcast 5?: instruction[3:0] 1?: a[9:8] 110 channel address register (car) 7?: a[7:0] 101 soft_sync control register (write only) 7: pn_en 6: test_mux_select 5: hop 4: start 3: sync 3 2: sync 2 1: sync 1 0: sync 0 100 pin_sync control register (write only) 7: toggle ien for bist 6: first sync only 5: hop_en 4: start_en 3: sync_en 3 2: sync_en 2 1: sync_en 1 0: sync_en 0 011 sleep (write only) 7?: reserved 5: access input port co ntrol registers 4: serial read 0 3: sleep 2: sleep 2 1: sleep 1 0: sleep 0 010 data register 2 (dr2) 7?: reserved 3?: d [19:16] 001 data register 1 (dr1) 15?: d [15:8] 000 data register 0 (dr0) 7?: d [7:0] table xii. microport instructions instruction comment 0000 all chips and all channels will get the access. 0001 channel 0, 1, 2 of all chips will get the access. 0010 channel 1, 2, 3 of all chips will get the access. 0100 all chips will get the access. * 1000 all chips with chip_id[3:0] = xxx0 will get the access. * 1001 all chips with chip_id[3:0] = xxx1 will get the access. * 1100 all chips with chip_id[3:0] = xx00 will get the access. * 1101 all chips with chip_id[3:0] = xx01 will get the access. * 1110 all chips with chip_id[3:0] = xx10 will get the access. * 1111 all chips with chip_id[3:0] = xx11 will get the access. * * a[9:8] bits control which channel is decoded for the access.
rev. b ad6624 e34e external memory map when broadcast is enabled (bit 6 set high), readback is not valid because of the potential for internal bus contention. therefore, if readback is subsequently desired, the broadcast bit should be set low. bits 1? of this register are address bits that decode which of the four channels are being accessed. if the instruction bits decode an access to multiple channels, these bits are ignored. if the instruction decodes an access to a subset of chips, the a[9:8] bits will otherwise determine the channel being accessed. channel address register (car) this register represents the 8-bit internal address of each channel. if the autoincrement bit of the acr is 1, this value will be i ncre- m ented after every access to the dr0 register, which will in t urn access the location pointed to by this address. the channel address register cannot be read back while the broadcast bit is set high. soft_sync control register external address [5] is the soft_sync control register and is write only. bits 0? of this register are the soft_sync control bits. these pins may be written to by the controller to initiate the synchro- n ization of a selected channel. although there are four inputs, these do not necessarily go to the channel of the same number. this is fully configurable at the channel level as to which bit to l ook at. all four channels may be configured to synchronize from a single position, or they may be paired or all independent. b it 4 determines if the synchronization is to apply to a chip start. if this bit is set, a chip start will be initiated. bit 5 determines if the synchronization is to apply to a chip hop. if this bit is set, the nco frequency will be updated when the soft_sync occurs. bit 6 configures how the internal databus is configured. if this bit is set low, the internal adc databuses are configured nor- mally. if this bit is set, the internal test signals are selected. the internal test signals are configured in bit 7 of this register. bit 7 if set clear, a negative full-scale signal is generated and made available to the internal databus. if this bit is high, inter- nal pseudo-random sequence generator is enabled and this data is available to the internal databus. the combined functions of bits 6 and 7 facilitate verification of a given filter design and in co njunction w ith the misr registers, allow for detailed in-system chip testing. in conjunction with the jtag test board, very high l evels of chip veri fication can be done du ring system test, in both the factory and field. pin_sync control register external address [4] is the pin_sync control register and is write only. bits 0? of this register are the sync_en control bits. these pins may be written to by the controller to allow pin synchroni- zation of a selected channel. although there are four inputs, these do not necessarily go to the channel of the same number. this is fully configurable at the channel level as to which bit to look at. all four channels may be configured to synchronize from a single position, or they may be paired or all independent. bit 4 determines if the synchronization is to apply to a chip start. if this bit is set, a chip start will be initiated pin_sync occurs. bit 5 determines if the synchronization is to apply to a chip hop. if this bit is set, the nco frequency will be updated when the pin_sync occurs. b it 6 is used to ignore repetitive synchronization signals. in so me applications, this signal may occur periodically. if this bit is clear, each pin_sync will restart/hop the channel. if this bit is set, only the first occurrence will cause the chip to take action. bit 7 is used with bits 6 and 7 of external address 5. when this bit is cleared, the data supplied to the internal databus simulates a normal adc. when this bit is set, the data supplied is in the form of a time-multiplexed adc such as the ad6600 (this allows the equivalent of testing in the 4-channel input mode). internally, when set, this bit forces the ien pin to toggle as if it were driven by the a/b signal of the ad6600. sleep control register external address [3] is the sleep register. bits 3? control the state of each of the channels. each bit corre- sponds to one of the possible rsp channels within the device. if this bit is cleared, the channel operates normally. however, when this bit is set, the indicated channel enters a low-power sleep mode. table xiii. memory map for input port control registers ch address register bit width comments 00 lower threshold a 10 9?: lower threshold for input a 01 upper threshold a 10 9?: upper threshold for input a 02 dwell time a 20 19?: minimum time below lower threshold a 03 gain range a control register 5 4: output polarity lia-a and lia-b 3: interleaved channels 2?: linearization hold-off register 04 lower threshold b 10 9?: lower threshold for input b 05 upper threshold b 10 9?: upper threshold for input b 06 dwell time b 20 19?: minimum time below lower threshold b 07 gain range b control register 5 4: output polarity lib-a and lib-b 3: interleaved channels 2?: linearization hold-off register
rev. b ad6624 e35e bit 4 causes the normal rsp data on serial channel 0 to be r eplaced with read access data. this allows reading the internal registers over the serial bus. it should be noted that in the mode, any rsp data will be superceded by internal access data. bit 5 allows access to the input control port registers at channel addresses 00-07. when this bit is set low, the normal memory map is accessed. however, when this bit is set, it allows access to the input port control registers. access to these registers allows the lower and upper thresholds to be set along with dwell time and other features. when this bit is set, the value in exter- nal address 6 (car) points to the memory map for the input port control registers instead of the normal memory map. see input port control registers below. bits 6? are reserved and should be set low. data address registers external address [2-0] form the data registers dr2, dr1, and dr0 respectively. all internal data words have widths that are less than or equal to 20 bits. accesses to external address [0] dr0 trigger an internal access to the ad6624 based on the add ress indicated in the acr and car. thus during writes to the inter- nal registers, external address [0] dr0 must be written l ast. at this point, data is transferred to the internal memory i ndi- cated in a[9:0]. reads are performed in the opposite direction. once the address is set, external address [0] dr0 must be the first data register read to initiate an internal access. dr2 is only four bits wide. data written to the upper four bits of this register will be ignored. likewise reading from this register will produce only four lsbs. write sequencing writing to an internal location is achieved by first writing the upper two bits of the address to bits 1 through 0 of the acr. bits 7:2 may be set to select the channel as indicated above. the c ar is then written with the lower eight bits of the internal address (it does not matter if the car is written before the acr as long as both are written before the internal access). data r egister 2, (dr2) and data register 1 (dr1) must be written first because the write to data register dr0 triggers the internal access. data register dr0 must always be the last register written to initiate the internal write. read sequencing r eading from the microport is accomplished in the same manner. the internal address is set up the same way as the write. a read from data register dr0 activates the internal read, thus register dr0 must always be read first to initiate an internal read fol- lowed by dr1 and dr2. this provides the eight lsbs of the internal read through the microport (d[7:0]). additional data registers can be read to read the balance of the internal memory. read/write chaining the microport of the ad6624 allows for multiple accesses w hile cs ( cs )t wr rd e t cs , rd , wr ,de t t de(de,de) cs , rd , wr () dead t cs , rd ( ds ), wr (rw)trd( dtack ) rd( dtack ) s s () dead t cs, ds ( rd ),rw( wr )t dtack (rd) dtack (rd) ds ( rd )s cr t d , t (sr) car() raa,a, a acat ,, , acat , ,(aa a) acat ,, aw , , aca bit 4 determines the polarity of lia-a and lia-b. if this bit is cleared, the li signal is high when the upper threshold has been e xceeded. however, if this bit is set, the li pin is low when active. this allows maximum flexibility when using this function.
rev. b ad6624 e36e b it 3 determines if the input consists of a single channel or tdm channels such as when using the ad6600. if this bit is c leared, a single adc is assumed. in this mode, lia? functions as the active output indicator. lia? provides the complement of lia?. however, if this bit is set, the input is determined to be dual channel and determined by the state of the iena pin. if the iena pin is low, the input detection is directed to lia?. if the iena pin is high, the input is directed to liab. in either case, bit 4 determines the actual polarity of these signals. bits 2? determine the internal latency of the gain detect func- tion. when the lia?, b pins are made active, they are typically used to change an attenuator or gain stage. since this is prior to t he adc, there is a latency associated with the adc and with the s ettling of the gain change. this register allows the internal delay of the lia?, b signal to be programmed. addresses 4? duplicate address 00?3 for input port b (inb[13:0]). serial port control the ad6624 will have four serial ports serving as primary data output interfaces. in addition to output data, these ports will provide control paths to the internal functions of the ad6624. serial port 0 (sdin0) can access all of the internal registers for a ll of the channels while ports 1, 2, and 3 (sdin1?) are limited to their local registers only. in this manner, a single dsp could be used to control the ad6624 over the serial port 0 interface. the option is present to use a dsp per channel if needed. in addition to the global access of serial port 0, it has preemptive access over the other serial ports and the microport. the serial output and input functions use mainly separate hardware and can largely be considered separate ports that use a common serial clock (sclk). the serial input port is self- f raming as described below and allows more efficient use of the serial i nput bandwidth for programming. hence, the state of the sdfs signal has no direct impact on the serial input port. since the serial input port is self-framing, it is not necessary to wait for an sdfs to perform a serial write. the beginning of a serial input frame is signaled by a frame bit that appears on the sdi pin. this is the msb of the serial input frame. after the frame bit has been sampled high on the falling edge of s clk, a state counter will start and enable an 11-bit serial shifter four serial clock cycles later. these four sclk cycles represent the ?on? care?bits of the serial frame that are ignored. after all of the bits are shifted, the serial input port will pass along the 8-bit data and 3-bit address to the arbitration block. the serial word structure for the sdi input is illustrated in the table below. only 15 bits are listed so that the second bit in a standard 16-bit serial word is considered the frame bit. this is done for compatibility with the ad6620 serial input port. the shifting order begins with frame and shifts the address msb first and then the data msb first. jtag boundary scan the ad6624 supports a subset of ieee standard 1149.1 spec ifi- cations. for additional details of the standard, please see ?eee st andard test access port and boundary-scan archite cture, ieee-1149 publication from ieee. the ad6624 has five pins associated with the jtag interface. these pins are used to access the on-chip test access port and are listed in the table below. all input jtag pins are pull-up, except for tclk which has a pull-down. table xiv. boundary scan test pins name pin number description trst tar tck tc ts tas td td td td tadt ta t sc c dcde ass saeread etest ca tc dcde t dc s s d asda d, rae a a a d d d d d d d d sck sd ck rae ss s sct
rev. b ad6624 e37e extest (3?b000) places the ic into an external boundary-test mode and selects the boundary-scan register to be co nnected between tdi and tdo. during this, the boundary-scan regis- ter is accessed to drive test data off-chip via boundary outputs and receive test data off-chip from boundary inputs. idcode (3?b001) allows the ic to remain in its functional mode and selects device id register to be connected between tdi a nd tdo. accessing the id register does not interfere with the operation of the ic. sample/preload (3?b010) allows the ic to remain in normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. the boundary-scan register can be accessed by a scan operation to take a sample of t he functional data entering and leaving the ic. also, test data can be preloaded into the boundary scan register before an extest instruction. h ighz (3?b011) sets all outputs to high impedance state. selects the 1-bit bypass register to be connected between tdi and tdo. clamp (3?b100) sets the outputs of the ic to logic levels determined by the boundary-scan register and selects the 1-bit bypass register to be connected between tdi and tdo. before this instruction, boundary-scan data can be preloaded with the s ample/preload instruction. bypass (3?b111) allows the ic to remain in normal functional mode and selects 1-bit bypass register between tdi and tdo. during this instruction, serial data is transferred from tdi to tdo without affecting operation of the ic. internal write access up to 20 bits of data (as needed) can be written by the process described below. any high order bytes that are needed are writ- ten to the corresponding data registers defined in the external 3-bit address space. the least significant byte is then written to dr0 at address (000). when a write to dr0 is detected, the internal microprocessor port state machine then moves the data in dr2-dr0 to the internal address pointed to by the address in the lar and amr. write pseudocode void write_micro(ext_address, int data); main(); { / * this code shows the programming of the nco phase offset register using the write_micro function as defined above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. internal address = 0x087 * / // holding registers for nco phase byte wide access data int d1, d0; // nco frequency word (16-bits wide) nco_phase = 0xcbef; // write acr write_micro(7, 0x03); // write car write_micro(6, 0x03); // write dr1 with d[15:8] d1 = (nco_phase & 0xff00) >> 8; write_micro(1, d1); // write dr0 with d[7:0] // on this write all data is transferred to the internal address d0 = nco_freq & 0xff; write_micro(0, d0); } // end of main internal read access a read is performed by first writing the car and amr as with a write. the data registers (dr2edr0) are then read in the reverse order that they were written. first, the least significant byte of the data (d[7:0]) is read from dr0. on this transaction, the high bytes of the data are moved from the internal address pointed to by the car and amr into the remaining data regis- ters (dr2edr1). this data can then be read from the data registers using the appropriate 3-bit addresses. the number of data registers used depends solely on the amount of data to be read or written. any unused bit in a data register should be masked out for a read. read pseudocode int read_micro(ext_address); main(); { / * this code shows the reading of the first rcf coefficient using the read_micro function as defined above. the variable address is the external address a[2..0]. internal address = 0x000 * / // holding registers for the coefficient int d2, d1, d0; // coefficient (20-bits wide) long coefficient; // write amr write_micro(7, 0x00); // write lar write_micro(6, 0x00); / * read d[7:0] from dr0, all data is moved from the internal registers to the interface registers on this access * / d0 = read_micro(0) & 0xff; // read d[15:8] from dr1 d1 = read_micro(1) & 0xff; // read d[23:16] from dr2 d2 = read_micro(2) & 0x0f; coefficient = d0 + (d1 << 8) + (d2 << 16); } // end of main
rev. b ad6624 e38e outline dimensions 128-lead metric quad flat package [mqfp] (s-128-1) dimensions shown in millimeters top view (pins down) 1 38 39 65 64 102 128 103 0.27 0.17 0.50 bsc 1.03 0.88 0.73 seating plane 3.40 max coplanarity 0.10 max 0.50 0.25 2.90 2.70 2.50 17.45 17.20 16.95 14.20 14.00 13.80 20.20 20.00 19.80 23.45 23.20 22.95
rev. b ad6624 e39e revision history location page 3/04?data sheet changed from rev. a to rev. b. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 updated pub code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9/02?data sheet changed from rev. 0 to rev. a. edits to example filter response section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 edits to scaling with floating-point or gain-ranging adcs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edits to cic5 rejection section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 edits to table vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 edits to start section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 edits to serial data frame (serial cascade) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 realignment of comments in table viii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 edits to pin_sync control register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 addition of text to jtag boundary scan section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
e40e c02395e0e3/04(b)

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